`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:39:19 03/20/2014
// Design Name:   SBox
// Module Name:   C:/Users/C4U01/Desktop/SBoxCipher/SBox_tb.v
// Project Name:  SBoxCipher
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: SBox
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module SBox_tb;

	// Inputs
	reg [7:0] data_in1;
	reg [7:0] data_in2;
	reg sel;

	// Outputs
	wire [7:0] data_out1;
	wire [7:0] data_out2;

	// Instantiate the Unit Under Test (UUT)
	SBox uut (
		.data_in1(data_in1), 
		.data_in2(data_in2), 
		.data_out1(data_out1), 
		.data_out2(data_out2),
		.sel(sel)
	);

	initial begin
		// Initialize Inputs
		data_in1 = 0;
		data_in2 = 0;
		sel = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		data_in1 = "a";
		data_in2 = "c";
		#100;
		sel = 1;
		#100;
		data_in1 = "F";
		sel = 0;
		#100;
		$finish;

	end
	
endmodule

